The present invention pertains generally to integrated circuits, and more particularly to a termination technique for internal integrated circuit busses with local process/voltage/temperature compensation.
Integrated circuits communicate with one another using digital signals. In a binary system, the digital state of zero (xe2x80x9c0xe2x80x9d, logic xe2x80x9clowxe2x80x9d) is represented by the range of voltages between a minimum voltage VMIN (e.g., 0 volts) of the potential voltage range of the signal and a voltage VLOW that is low relative to the total range of voltage. The digital state of one (xe2x80x9c1xe2x80x9d, logic xe2x80x9chighxe2x80x9d) is represented by the range of voltages between a voltage VHIGH that is high relative to the total range of voltages and a maximum voltage VMAX (e.g., 1.5 volts) of the potential voltage range of the signal.
Because the signals are actually analog when transmitted over circuit transmission lines, the transition between digital states does not occur instantaneously, but instead occurs over a period of time that is dependent on physical conditions such as the parasitic resistance, inductance, and capacitance of the transmission line. The amount of time it takes to propagate a signal from one end of a transmission line to the other end of the transmission line is known as xe2x80x9cpropagation delayxe2x80x9d. Propagation delay is affected by the characteristic resistance, capacitance, and inductance of the metal used to construct the transmission line; accordingly, since the characteristic resistance, capacitance, and inductance of a line is dependent not only on the chemical and molecular properties of the metal used to form the transmission line, but also on the length, width, and thickness of the metal, propagation delay is therefore directly affected by the length and width of the line.
Functional circuit elements often operate on data that comprises multiple signals. For example, a circuit element may operate on a 16-bit data word. In order for the circuit element to complete the operation, all 16 bits must typically be available before the operation can be performed. Multiple-bit signals are typically transmitted in parallel over a multiple-transmission-line signal bus.
Variations in the lengths and widths of the individual transmission lines of a signal bus can result in non-synchronous arrival times of the individual bit signals at the receiving end of the bus. This phenomenon can result in undesirable signal jitter.
One method of improving signal integrity and arrival time skew of individual signal bits of a multiple-bit data bus is by equalizing the propagation delay between each of the transmission lines in the bus. Equalization may be achieved by inserting an appropriate number of repeaters along the various individual transmission lines such that each line is subject to approximately the same delay. Of course, the mere inclusion of a repeater along the transmission line results in some unavoidable minimum delay time. The minimum delay between the transmission of a signal and its receipt at the receiving end of the transmission line is often referred to as the insertion delay of the transmission line.
Insertion delay is an important property to consider in the design of transmission lines. Insertion delay is especially important when dealing with high frequency circuit operation because a long insertion delay can prevent the signal from being transmitted across a transmission line within a single (or other chosen integer number) clock cycle. If the insertion delay cannot be reduced enough to allow the signal to be transmitted over the line within a single clock cycle, then the signal takes twice (or even more times) as long to be transmitted over the bus, thereby effectively cutting the operating frequency of the bus in half (or less). Accordingly, minimizing the insertion delay is critical.
The insertion of repeaters along the transmission line can be problematic. First, the addition of repeaters along a transmission line essentially generates a subset of shorter transmission lines, each corresponding to a segment of the whole. Because each individual segment of the transmission line is itself merely a shorter transmission line, each segment will therefore exhibit transmission line properties such as propagation delay and signal reflections as well, albeit on a smaller scale.
Second, it is well-known that unless the impedance of a transmission line matches the impedance of the load it drives, a signal transmitted along the line will degrade due to signal reflections at the load. Accordingly, the repeater terminating each individual segment of the transmission line generates additional signal reflections.
Another difficulty in meeting satisfactory transmission line design requirements is that the operating characteristics of transistors such as CMOS transistors, from which integrated circuit signal drivers/receiver/repeaters are typically constructed, change under a variety of conditions, often referred to as process, voltage, temperature (PVT) variations. More specifically, the operating characteristics due to PVT variations may change with variations in manufacturing process (which can result in variations in the length L or width W dimensions of the transistors) as well as with variations in operating conditions such as junction temperature and supply voltage levels. The operating characteristics may also change with variations of voltage differences across the transistor terminals. If inadequate compensation is made for these variations, the output slew rate and output impedance of the driver/receiver/repeater may vary substantially along a particular transmission line as well as from transmission line to transmission line on a chip.
As is known in the art, complementary CMOS inverters are commonly used as repeaters along long transmission lines. FIG. 1 illustrates a complementary CMOS inverter 10. As illustrated, the complementary CMOS inverter 10 includes a p-channel field effect transistor (PFET) 12 with a source connected to a high power supply VDD, a gate connected to an inverter input node 16, and a drain connected to an inverter output node 18. The complementary CMOS inverter 10 also includes an n-channel field effect transistor (NFET) 14 with a source connected to a low voltage source (e.g., ground), a gate connected to the inverter input node 16, and a drain connected to the inverter output node 18.
The transfer characteristic of the CMOS inverter of FIG. 1 is shown in FIG. 2. The transfer characteristic plots VOUT over VIN for the range of values of VIN. It is known in the art that if the threshold voltage VT for both the PFET and NFET is identical, VOUT may be defined as:
xe2x80x83VOUT=VIN+VT+[(VIN+VT)2+VDD(VDDxe2x88x922VINxe2x88x922VT)xe2x88x92(VINxe2x88x92VT)2]1/2,
where VIN is the input voltage, and VDD is the power supply voltage. As shown, in the ideal case, the inverter switches when VIN=VDD/2.
As shown in FIG. 2, the transfer characteristic of the inverter is affected by the proportionality constants xcex2p and xcex2n of the respective PFET 12 and NFET 14. The proportionality constants xcex2p and xcex2n are dependent on the doping, construction, and dimensions (width W and length L) of the transistor. Accordingly, since the proportionality constants xcex2p and xcex2n may vary from one manufacturing process to another and even between localized areas of the chip within the same process, the transfer characteristic may be different across different chips manufactured in different groups and between localized areas of the same chip.
The transfer characteristic illustrates the effect of the proportionality constant ratio xcex2p/xcex2n on the switching point (also called the xe2x80x9ctrigger pointxe2x80x9d) of the inverter 10. As illustrated in FIG. 2, an inverter whose proportionality constant ratio xcex2p/xcex2n is 10 switches at a much lower input voltage VIN than an inverter whose proportionality constant ratio xcex2p/xcex2n is 0.1.
The transfer characteristic is also affected by the temperature of the inverter devices. As the temperature of the devices increases, the effective carrier mobility xcexc decreases, resulting in a decreased xcex2 for the devices. Thus, the overall transfer characteristic of the inverter shifts to the left as temperature increases and shifts to the right as the temperature decreases.
PVT variations may be conceptualized as a box, shown in FIG. 3, across which the operating characteristics of the transistors move. One of ordinary skill in the art will appreciate that the three characteristics, process, voltage and temperature can be visualized as a three dimensional graph with a xe2x80x9cslow cornerxe2x80x9d identifying a point when the three characteristics most fully affect operating conditions, and a xe2x80x9cfast cornerxe2x80x9d identifying a point when the three characteristics do not greatly affect operating conditions. For example, the operating characteristics may move from a fastest corner of PVT variations to a slowest corner of PVT variations, and everywhere in between.
As described above, PVT variations affect the switching point of CMOS inverters used to implement repeaters along a transmission line. When a transmission line is optimized for operation at a nominal voltage, any change in PVT conditions will therefore affect the switching speed of the repeaters, which in turn affects the insertion delay of the transmission line. Accordingly, a need exists for a technique for ensuring consistent repeater switching speed despite variations in process, temperature and voltage.
A need also exists for maintaining high signal integrity when the transmission line is segmentized by repeaters.
The present invention is a technique for ensuring consistent repeater switching speed along a transmission line despite variations in process, temperature and voltage. Terminating repeaters are inserted along the transmission line to reduce the delay of the transmitted signal. Each terminating repeater includes a repeater and an associated termination circuit. Preferably each repeater is formed using at least one PFET and one NFET and has a metastability point centered around VDD/2 in the nominal case. An active termination circuit is positioned in close proximity to each repeater in order to prevent additional signal reflections generated by the repeater. The termination circuit is implemented with at least one PFET and one NFET, having identical transistor gate lengths as the PFET(s) and NFET(s) of the repeater. The termination circuit PFET and NFET are each ratioed to vary similarly to variations in the PFET and NFET of the repeater due to PVT variations. PVT variations shift the repeater""s metastability point. The active termination scheme shifts with PVT conditions such that the DC voltage at the repeater node positively tracks the metastability point of the repeater, thereby allowing for more consistent switching speeds despite PVT variation.